There exist several types of semiconductor device packages already in the market, in which one of them is a ball grid array package. The ball grid array package is generally used to form high I/O connections among dense electronic components and electronic circuits. Due to rapid advance of the fabrication technology, a current ball grid array package may have several thousands of driving and driven elements.
The increase in number of electronic components within a unit of the mounting surface results in narrowing of the circuits in width, which, in turn, may result in high heat resistance in the circuits. In the case that the heat generated by these components within the semiconductor device package cannot be dissipated effectively, the service life of the semiconductor device package would be definitely shortened.
FIG. 1 shows a conventional ball grid array package (a multi-layer member) to include two signal plane layers 2, a ground plane layer 4 and a power plane layer 6. In order to prevent signal interference between conductive patterns, insulated layers 8 and 10 are interposed to separate the signal plane layers 2, the ground plane layer 4 and the power plane layer 6. For example, the insulated layers 8 and 10 may be made of glass fibers, an FR4 standard laminate or an epoxy resin. As illustrated in FIG. 2, the ball grid array package defines a chip-interposed region 14 at a central portion thereof for receiving an integrated chip.
In general, the through holes 12 can be fabricated within the chip-interposed region 14 in an array manner. FIG. 2 shows typical positions of the through holes 12 in the ground plane layer. The outermost portion of the chip-interposed region 14 is designed in such a manner to have at least a ring of through holes 12 for signal transmission between the signal plane layers and the power connection. The inner portion of the chip-interposed region 14 is designed for connection with the ground and power plane layers. Upon such an arrangement, the outermost ring of through holes 12 in the chip-interposed region 14 of the ground plane layer disposes a plurality of clearance of the through holes in order to insulate the through holes 12 and the ground plane layer. It is noted that the clearances of the through holes (or the clearance of vias) can be formed by etching the ground plane layer. In the etching process, copper foil layers (signal and ground layers) may have manufacture error (non-uniform clearance) in locations of the holes, and thus the heat-dissipation path along the copper material between any two adjacent holes is quite possible to be deformed by possible error locations of the holes.
The circuits within the chip-interposed region 14 in the conventional ball grid array package 16 are so densely located and since the heat dissipating paths may be somehow interrupted by the presence of the clearances of through holes at the outermost ring portion of the chip-interposed region 14, the heat generated in the conventional ball grid array package 16 may be dissipated ineffectively to the exterior via the ground plane layer. In addition, the densely locations of the through holes 12 may minimize the surface area of the ground plane layer and thus consequently affect the effective paths of the GND to the chip, which will thereby decrease the signal quality.
FIG. 3 shows the position of the through holes within the chip-interposed region in the power plane layer with respect to that shown in FIG. 2. The clearances of through holes 12 in the outermost ring of the chip-interposed region 14 of FIG. 2 serve as the conductive through holes in the power plane layer in FIG. 3.